Integrated circuits ("ICs") are fabricated on a semiconductor substrate that is mounted within a typically epoxy or ceramic overmold for later mounting on a printed circuit board ("PCB"). As fabrication techniques improve, ICs tend to include circuits with increased complexity and increased number of input and output leads ("pinouts"). Further, as more transistors are fabricated on an IC die of a given size, dissipating heat from the IC becomes a greater challenge.
One packaging system for providing an IC with a large number of pinouts in a relatively small package area is known as the ball grid array ("BGA") package. FIG. 1 depicts a standard two-layer BGA mounting system, similar to the so-called OMNI.TM. system promoted by Motorola, Inc. In this system, a BGA package 2 includes a double-sided copper clad printed circuit board ("PCB") 4 with conductive and/or thermal vias 6A, 6B, 6C connecting upper BGA package conductive traces 8A, 8B, 8C to lower BGA package conductive traces 10A, 10B, 10C. The 8A traces and the 8B traces may each be donut-shaped, as may the corresponding 10A and 10B traces. The various vias preferably are identical and may be referred to interchangeably as conductive or thermal vias.
The BGA package further includes the IC die 12 to be packaged, and a plurality of meltable solder balls 14A, 14B, 14C in contact with the lower conductive traces 10A, 10B, 10C. The upper and lower BGA package traces 8A, 8B, 8C, 10A, 10B, 10C are typically formed by etching the copper clad upper and lower surfaces of BGA PCB 4. An overmold, shown in phantom as 16, encapsulates and thus protects the IC die 12. Overmold 16 could, of course, be sized to extend over a greater or lesser portion of the upper surface of BGA package 2 than what is depicted in FIG. 1.
Package 2 will eventually be soldered to a system printed circuit board ("PCB") 18, whose upper surface includes conductive traces 20A, 20B, 20C that will contact various of the solder balls 14A, 14B, 14C. Thus, while FIG. 1 shows BGA package 2 and system PCB 18 spaced apart vertically, in practice the solder balls and the system PCB traces are placed in contact with one another, whereupon an infrared reflow process melts the solder balls. Upon melting, the solder balls electrically and mechanically join various of the BGA package traces 10A, 10B, 10C to various of the system PCB traces 20A, 20B, 20C. The various solder balls may be arrayed in a relatively dense matrix, with adjacent balls being spaced-apart horizontally perhaps 0.050" to 0.060" (1.3 mm to 1.5 mm). As a result, BGA package 2 can advantageously provide a dense pattern of pinout connections with IC 12.
Those skilled in the art will appreciate that IC 12 may include various semiconductor devices such as bipolar or metal-oxide-semiconductor ("MOS") transistors, as well as effective resistor and capacitor components. These transistors and components will form one or more circuits that are typically coupled to an upper power source Vdd, and to a lower power source Vss (usually ground).
Bonding wires such as 22, 24 make electrical connection from pads formed on IC 12 (not shown) to a BGA package trace Or plane formed by etching the copper clad on the upper surface of BGA structure 2. Bond wire 22, for example, connects to a BGA package Vdd upper plane trace 8A that connects to a conductive via 6A, which connects to a BGA package Vdd lower plane trace 10A that connects to a solder ball 14A. On the underlying system PCB 18, one or more system PCB traces 20A couple to the Vdd power source that is connected to the system PCB 18. In similar fashion, one or more bond wires (not shown) will couple IC 12 to Vss on the system PCB 18.
Similarly, bonding wire 24 is shown coupled to an upper signal BGA package trace 8B that is connected to vias 6B, to BGA package lower signal trace 10B, and signal solder balls 14B. On system PCB 18, system PCB traces 20B couple electrical signals to or from IC 12. Other bonding wires will also be present but are not shown for ease of illustration. Of course, IC 12 will generally be coupled by various bond wires, upper BGA package traces, vias, lower BGA package traces to various different signal solder balls, for contact with various system PCB 18 signal traces.
As shown in FIG. 1, the lower substrate surface of IC 12 is connected to a BGA package IC die Vss plane 8C, that connects through several vias 6C to a BGA package lower surface Vss plane 10C to which solder balls 14C are attached. As noted, Vss connections to IC 12 generally are also brought out through Vss IC pads, bond wires, traces, vias, traces and solder balls in a manner similar to what is described herein with respect to the connections for Vdd. The underlying system PCB 18 includes a system PCB Vss ground plane 20C that electrically connects to such Vss solder balls, including solder balls 14C.
BGA package 2 is relatively economical to manufacture because PCB 4 may be a symmetrical and relatively inexpensive generic commodity. By symmetrical, it is meant that PCB 4 is manufactured with copper clad on the upper and lower surfaces of a typically epoxy glass core 22, commonly referred to as FR4 material. (It is from this copper clad that the upper and lower BGA package traces or planes 8A, 8B, 8C, 10A, 10B, 10C are formed.) Alternatively, core 22 may be fabricated from an adhesive-like resin commonly termed pre-preg.
It is important that PCB 4 be sufficiently rigid so that the various solder balls will register properly for soldering to corresponding system PCB traces. As a result, the vertical thickness of core 22 in FIG. 1 will typically be at least 0.02" to 0.03" (0.5 mm to 0.8 mm).
Although the BGA configuration of FIG. 1 has the advantage of being inexpensive to fabricate, it has several shortcomings. Specifically, BGA 4 does not provide a good signal plane for current surges into or out of IC 12, and does not do a good job of dissipating heat generated by IC 12. The relatively poor electrical and thermal performance associated with BGA structure 4 is especially apparent when IC 12 includes high density, high frequency digital circuitry. Essentially these performance shortcomings arise because the efficient system Vss and Vdd planes on PCB 18 are too far away from IC 12 to be truly effective.
Thermally, although the system PCB Vss plane 20C can sink heat dissipated by IC 12 and down-conducted through vias 6C, the system PCB Vss plane is just too remote for good dissipation. The prior art configuration of FIG. 1 has a thermal resistance .theta..sub.ja of about 35.degree. C./W, which means that for an increase of one watt dissipation, the junction temperature of the IC die 12 will increase 35.degree. C. As a result, IC 12 may overheat, or require bulky and relatively expensive heat sinking. Alternatively, IC 12 may have to be operated at a lower equivalent duty cycle to reduce dissipation, thus sacrificing IC 12 performance because of the poor thermal characteristics associated with prior art two-layer BGA packages.
Electrically, the current paths from the system PCB Vdd plane 20A, up into IC 12, through the system Vss plane 20C, and vice versa, are simply too long. As will be described, these long path lengths can result in the Vdd and Vss potentials within IC 12 impermissibly varying in magnitude during current surges. What occurs is that an effective inductance L exists in series with the relatively long power supply current paths. Large mutual inductances may be present that force some transient surge ground current to return undesirably through IC 12, rather than through the system PCB planes. This IC 12 transient surge current flow can cause ground bounce and crosstalk between various circuits within IC 12. In addition, the effective inductance L can contribute to an undesirable time delay for signals propagating through IC 12.
More specifically, an excessively long path between a signal node on the IC chip and a signal return ground plane increases the effective series inductance (L) therebetween. In the presence of current spikes through such path, the voltage at the Vss pad(s) and/or Vdd pad(s) within IC 12 can deviate or "bounce" from their nominal DC voltage.
Consider, for example, the effect of a relatively long current return path for a high speed CMOS digital circuit fabricated within IC 12. The output of circuit typically will include a PMOS pull-up and an NMOS pull-down transistor coupled in series between Vdd and Vss. When outputting a digital "1", the NMOS transistor is off, and the PMOS transistor is on, and the circuit sources current from Vdd through the PMOS transistor to an output load coupled to Vss. When outputting a digital "0", the PMOS transistor is off, the NMOS transistor is on and sinks current from the output load.
But when this CMOS circuit changes states from "1" to "0" or vice versa, for a brief interval the PMOS and NMOS transistors may both be simultaneously on due to imperfect switching. When both transistors are on during transitions a rapid change (or "spike") in current (di/dt) through the circuit can occur. In the presence of series inductance L, current spiking results in an L di/dt.apprxeq.dV/dt change or "bounce" in the voltage present at the Vdd and/or Vss pads on IC 12. Ground bounce results from this dV/dt for Vdd and/or Vss within IC 12.
Such voltage bouncing within IC 12 is especially troublesome at "0" to "1" transitions because CMOS transistors exhibit less noise immunity margin for error near "0" voltage states as contrasted to "1" voltage states. For this reason, it is especially important that a low inductance impedance Vss path within IC 12 be maintained.
In addition to producing overshoot and undershoot on output voltage waveforms, ground bounce can degrade digital switching reliability. This degradation occurs because any variations in Vdd or Vss within IC 12 can alter CMOS trip points.
Generally, the configuration of FIG. 1 will exhibit an output impedance between a signal output pad on IC 12 and Vss of about 250 .OMEGA.. A 250 .OMEGA. output impedance is undesirably high for matching to a system PCB that typically is characterized by an impedance in the 50 .OMEGA. to 75 .OMEGA. range. The resultant impedance mismatch contributes to overshoot and ringing on signals coupled from the BGA package to the system PCB. The configuration of FIG. 1 also exhibits an effective series inductance of perhaps 12 nh to 15 nh, and an equivalent output shunt capacitance at a signal output pad of about 1.2 pF.
As noted, the series inductance can produce overshoot and ringing in IC 12 signals, especially when a relatively light capacitive load is to be driven. Further, the series inductance and shunt capacitance associated with the two-layer BGA package of FIG. 1 can undesirably delay a signal passing through IC 12 by several nanoseconds. If IC 12 includes high speed switching devices (e.g., wherein the operating frequency is greater than perhaps 30 MHz), a BGA package-imposed time delay of a few nanoseconds may be unacceptable.
In summary, there is a need for a BGA package having improved thermal and electrical characteristics, especially for high speed digital ICs. To reduce ground bounce and enhance IC operating reliability, such BGA package should exhibit approximately 50 .OMEGA. output impedance and decreased effective series inductance. Further, it should be possible to manufacture such a BGA package using generic symmetrical PCB materials.
The present invention discloses such a BGA package.